A 2D integrated circuit package (2D IC package) is a single package constructed by mounting multiple semiconductor wafers/dies/chips and interconnecting them horizontally to function as a single device or system. A 3D integrated circuit package (3D IC package) or 3 dimensional stack integrated circuit package (3DS IC package) is a single integrated package constructed by stacking vertically separate semiconductor wafers/dies/chips and interconnecting them to function as a single device or system. In many designs, through-silicon via (TSV) technology enables the interconnections between the multiple semiconductor wafers/dies/chips and the resulting incorporation of substantial functionality into a relatively small package. As will be appreciated, the wafers/dies/chips may be heterogeneous. For reference, a 3D integrated circuit (3D IC) is a single wafer/die/chip having two or more layers of active electronic components integrated vertically and horizontally into a single circuit.
Recently, a different multi-die package has been developed. This type of package is sometimes referred to as a 2.5D integrated circuit package (2.5D IC package). In a 2.5D IC package, multiple wafers/dies/chips are mounted on an “interposer” structure. Multiple dies are placed on a passive silicon interposer which is responsible for the interconnections between the dies, as well as the external I/Os through the use of TSV technology. This design is superior to the 3D IC package due to lower cost and better thermal performance. As will be appreciated, each “die” can be a 2D IC package or even a 3D IC or 3D IC package.
Turning to FIG. 1, there is provided a cross-sectional diagram illustrating a conventional 2.5D IC package 100. The 2.5D IC package 100 includes multiple dies 102 having multiple electrical connections 110 (e.g., microbumps) to an interposer substrate 104 for carrying power, ground and/or other signals. The interposer substrate 104 may be constructed of any suitable material that provides multiple electrical conductors extending therethrough from one side to the other side. The interposer substrate 104 also includes multiple connections 112 (e.g., bumps) to a package substrate 106. Package substrate 106 includes multiple connections 114 (e.g., BGA solder balls).
Included within the interposer substrate 104 are a plurality of electrical conductor lines (not shown) extending therethrough and therein. The conductors are configured and structured to provide a desired interconnect pattern or matrix between and among the connections 110 and the connections 112. In one embodiment, the substrate 104 is a silicon interposer constructed using TSV technology.
Limited by the photolithography reticle size (masking and pattern size), the maximum silicon interposer substrate size that can be achieved is about 25 mm×31 mm. In potential high end network applications, if 2.5D IC packaging were to be used, multiple large flip-chip mounted dies would need to be placed side by side on the interposer substrate. This would require use of a larger interposer substrate (e.g. 45 mm×45 mm). However, this size of interposer substrate is either not readily manufactured or would require a specialized photolithography process which will significantly increase costs (and likely lower yield).
Accordingly, there is needed a method and interposer substrate packaging configuration to be used in manufacturing a multi-die package using conventional or current photolithography technology.